PATH DELAY FAULTS IN VLSI CIRCUITS : A STATISTICAL APPROACH

Mustapha  M. HAMAD

Delay testing is an essential element in the manufacturing of high quality VLSI digital circuits. Despite the considerable research which has already been reported, some significant problems remain to be solved in this area. Realistic algorithms for the detection and testing of delay faults have only emerged over the last few years; however, none of them has yet proved to be both comprehensive and cost‑effective. As a result, more work in the area of delay fault modeling/testing is not only justified, but is also essential.

Path delay faults effectively model delay defects in VLSI digital circuits. However, non‑robust tests for path delay faults are inherently unreliable. To overcome this obstacle, robust tests were developed. Unfortunately, robust tests often do not exist for many paths in practical circuits, thus leading to very poor logical path delay fault coverage.

Therefore, in an attempt to address these problems this dissertation investigates new approaches to improve the overall confidence of delay testing. We develop a comprehensive statistical model for path delay faults in VLSI circuits which effectively deals with multiple delay faults, thus eliminating the need for single fault assumption. We create a methodology to describe path failures using the newly developed model. We define a methodology for selecting a feasible test set for path delay testing which will serve as an alternative to the impractical method of exhaustively testing every path in the circuit. We perform analysis using these methodologies on a set of benchmark circuits. In addition, we automate the procedures used in the analysis.

Methodologies developed in this research could be integrated in a tool for evaluating both statistical and logical fault coverage and for performing path failure analysis on VLSI circuits. Moreover, results from our research will better enable the system designer to understand the strength of statistical modeling. Finally, we believe that our research is both timely and contributive in successfully dealing with several aspects of the rapidly growing area of delay fault modeling/testing.